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1 datasheet 12-bit, +3.3v, 260+msps, high speed d/a converter isl5857 the isl5857 is a 12-bit, 260+msps (mega samples per second), cmos, high speed, low power, d/a (digital-to-analog) converter designed specifically for use in high performance communication systems such as base transceiver stations utilizing 2.5g or 3g cellular protocols. this device complements the isl5x57 family of high speed converters, which include 10, 12, and 14-bit devices. applications ? cellular infrastructure - single or multicarrier: is-136, is-95, gsm, edge, cdma2000, wcdma, tds-cdma ? bwa infrastructure ? medical/test instrumentation ? wireless communication systems ? high resolution imaging systems ? arbitrary waveform generators features ? low power . . . . . . . . 103mw with 20ma output at 130msps ? adjustable full scale output current. . . . . . . . . 2ma to 20ma ? +3.3v power supply ? 3v lvcmos compatible inputs ? excellent spurious free dynamic range (73dbc to nyquist, f s = 130msps, f out = 10mhz) ? umts adjacent channel power = 70db at 19.2mhz ? edge/gsm sfdr = 90dbc at 11mhz in 20mhz window ? pin compatible, 3.3v, lower power replacement for the ad9752 and hi5860 ? pb-free (rohs compliant) d11 (msb) (1) d10 (2) d9 (3) d8 (4) d7 (5) d6 (6) d5 (7) d4 (8) d11 d10 d9 d8 d7 d6 d5 d4 dcom (26, 13, 14) clk (28) (24) av dd (22) iouta (21) ioutb (18) fsadj (16) reflo isl5857 dv dd (27) 0.1f 10f (20) acom 50 (15) sleep (17) refio 0.1f 1.91k ferrite 10h (23) comp 0.1f + bead r set d3 d2 d1 d0 d3 (9) d2 (10) d1 (11) d0 (lsb) (12) 0.1f 10h + bead (25, 19) nc acom dcom 10f +3.3v (v dd ) 50 (50) 1:1, z1:z2 one connection any 50 load represents figure 1. typical applications circuit october 7, 2015 fn6079.3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2004, 2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl5857 2 fn6079.3 october 7, 2015 submit document feedback functional block diagram pin configuration isl5857 28 ld soic/tssop top view upper voltage reference (lsb) d0 d1 d2 d3 d4 d5 d6 d9 clk d7 d8 5-bit decoder refio cascode current source switch matrix bias generation int/ext 38 38 31 msb segments 7 lsbs + comp iouta ioutb d10 d11 input latch reflo fsadj sleep figure 2. functional block diagram 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d11 (msb) d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 clk dcom nc av dd comp ioutb nc fsadj refio reflo sleep dv dd iouta acom dcom dcom
isl5857 3 fn6079.3 october 7, 2015 submit document feedback pin descriptions pin no. pin name description 1 through 12 d11 (msb) through d0 (lsb) digital data bit 11, (most significant bit) throug h digital data bit 0, (least significant bit). 15 sleep control pin for power-down mode. sleep mode is acti ve high; connect to ground for normal mode. sleep pin has internal 20a active pull-down current. 16 reflo connect to analog ground to enable internal 1.2v reference or connect to av dd to disable internal reference. 17 refio reference voltage input if internal reference is disabled . reference voltage output if internal reference is enabled. use 0.1f capacitor to ground when internal reference is enabled. 18 fsadj full scale current adjust. use a resistor to ground to adjust full scale output current. full scale output current = 32 x v fsadj /r set . 19, 25 nc no connect. these should be grounded, but can be left disconnected. 21 ioutb the complementary current output of the device. full sc ale output current is achieved when all input bits are set to binary 0. 22 iouta current output of the device. full scale output current is achieved when all input bits are set to binary 1. 23 comp connect 0.1f capacitor to acom. 24 av dd analog supply (+3.0v to +3.6v). 20 acom connect to analog ground. 26, 13, 14 dcom connect to digital ground. 27 dv dd digital supply (+3.0v to +3.6v). 28 clk clock input. ordering information part number ( notes 1 , 2 ) part marking temp range (c) package (rohs compliant) pkg. dwg. # clock speed isl5857ibz no longer available or supported, recommended replacement part: ISL5857IAZ isl5857ibz -40 to +85 28 ld soic m28.3 260mhz ISL5857IAZ isl 5857iaz -40 to +85 28 ld tssop m28.173 260mhz notes: 1. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 2. for moisture sensitivity level (msl), please see product information page for isl5857 . for more information on msl, please see tech brief tb363 .
isl5857 4 fn6079.3 october 7, 2015 submit document feedback absolute maximum rating s thermal information digital supply voltage dv dd to dcom . . . . . . . . . . . . . . . . . . . . . . . . +3.6v analog supply voltage av dd to acom. . . . . . . . . . . . . . . . . . . . . . . . . +3.6v grounds, acom to dcom . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v digital input voltages (d9-d0, clk, sleep) . . . . . . . . . . . . . . . dv dd + 0.3v reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . av dd + 0.3v analog output current (i out ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to 85c thermal resistance (typical, note 3 ) ? ja (c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 tssop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . . . . . -65c to 150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 3. ? ja is measured with the component mounted on an evaluation pc board in free air. see tech brief tb379 . electrical specifications av dd = dv dd = +3.3v, v ref = internal 1.2v, ioutfs = 20ma, t a = +25c for all typical values. boldface limits apply across the operating temperature range, -40c to +85c. parameter test conditions t a = -40c to 85c units min typ max system performance resolution 12 --bits integral linearity error, in l ?best fit? straight line ( note 10 ) -1.25 0.5 +1.25 lsb differential linearity error, dnl ( note 10 ) -1 0.5 +1 lsb offset error, i os iouta ( note 10 ) -0.006 +0.006 % fsr offset drift coefficient ( note 10 )-0.1-ppm fsr/c full scale gain error, fse w ith external reference ( notes 4 , 10 ) -3 0.5 +3 % fsr with internal reference ( notes 4 , 10 ) -3 0.5 +3 % fsr full scale gain drift wit h external reference ( note 10 ) - 50 - ppm fsr/c with internal reference ( note 10 ) - 100 - ppm fsr/c full scale output current, i fs 2 - 20 ma output voltage compliance range ( note 5 ) -1.0 - 1.25 v dynamic characteristics maximum clock rate, f clk 260 300 - mhz output rise time full scale step - 1.5 - ns output fall time full scale step - 1.5 - ns output capacitance -10 - pf output noise ioutfs = 20ma - 50 - pa/ ? hz ioutfs = 2ma - 30 - pa/ ? hz ac characteristics (using figure 15 with r diff = 50 and r load = 50 , full scale output = -2.5dbm ? spurious free dynamic range, sfdr within a window f clk = 210msps, f out = 80.8mhz, 30mhz span ( notes 6 , 10 )-73-dbc f clk = 210msps, f out = 40.4mhz, 30mhz span ( notes 6 , 10 )-80-dbc f clk = 130msps, f out = 20.2mhz, 20mhz span ( notes 6 , 10 )-85-dbc
isl5857 5 fn6079.3 october 7, 2015 submit document feedback spurious free dynamic range, sfdr to nyquist (f clk /2) f clk = 260msps, f out = 80.8mhz ( notes 6 , 10 )-47-dbc f clk = 260msps, f out = 40.4mhz ( notes 6 , 10 )-60-dbc f clk = 260msps, f out = 20.2mhz ( notes 6 , 10 )-62-dbc f clk = 210msps, f out = 80.8mhz ( notes 6 , 10) - 51 - dbc f clk = 210msps, f out = 40.4mhz ( notes 6 , 10 , 12 )-60-dbc f clk = 200msps, f out = 20.2mhz, t = 25c ( notes 6 , 10 ) 60 62 - dbc f clk = 200msps, f out = 20.2mhz, t = -40c to 85c ( notes 6 , 10 ) 58 --dbc f clk = 130msps, f out = 50.5mhz ( notes 6 , 10 )-57-dbc f clk = 130msps, f out = 40.4mhz ( notes 6 , 10 )-62-dbc f clk = 130msps, f out = 20.2mhz ( notes 6 , 10 )-69-dbc f clk = 130msps, f out = 10.1mhz ( notes 6 , 10 )-73-dbc f clk = 130msps, f out = 5.05mhz, t = 25c ( notes 6 , 10 ) 70 77 - dbc f clk = 130msps, f out = 5.05mhz, t = -40c to 85c ( notes 6 , 10 ) 68 --dbc f clk = 100msps, f out = 40.4mhz ( notes 6 , 10 )-60-dbc f clk = 80msps, f out = 30.3mhz ( notes 6 , 10 )-63-dbc f clk = 80msps, f out = 20.2mhz ( notes 6 , 10 )-69-dbc f clk = 80msps, f out = 10.1mhz ( notes 6 , 10 , 12 )-70-dbc f clk = 80msps, f out = 5.05mhz ( notes 6 , 10 )-76-dbc f clk = 50msps, f out = 20.2mhz ( notes 6 , 10 )-68-dbc f clk = 50msps, f out = 10.1mhz ( notes 6 , 10 )-73-dbc f clk = 50msps, f out = 5.05mhz ( notes 6 , 10 )-77-dbc spurious free dynamic range, sfdr in a window with eight tones f clk = 210msps, f out = 28.3mhz to 45.2mhz, 2.1mhz spacing, 50mhz span ( notes 6 , 10 , 12 ) -65 - dbc f clk = 130msps, f out = 17.5mhz to 27.9mhz, 1.3mhz spacing, 35mhz span ( notes 6 , 10 ) -68 - dbc f clk = 80msps, f out = 10.8mhz to 17.2mhz, 811khz spacing, 15mhz span ( notes 6 , 10 ) -75 - dbc f clk = 50msps, f out = 6.7mhz to 10.8mhz, 490khz spacing, 10mhz span ( notes 6 , 10 ) -77 - dbc spurious free dynamic range, sfdr in a window with edge or gsm f clk = 78msps, f out = 11mhz, in a 20mhz window, rbw = 30khz ( notes 6 , 10 , 12 ) -90 - dbc adjacent channel power ratio, acpr with umts f clk = 76.8msps, f out = 19.2mhz, rbw = 30khz ( notes 6 , 10 , 12 ) - 70 - db voltage reference internal reference voltage, v fsadj pin 18 voltage with internal reference 1.2 1.23 1.3 v internal reference voltage drift - 40 - ppm/c internal reference output current sink/source capability reference is not intended to be externally loaded - 0 - a reference input impedance -1 - m reference input multiplying bandwidth ( note 10 )-1.0-mhz electrical specifications av dd = dv dd = +3.3v, v ref = internal 1.2v, ioutfs = 20ma, t a = +25c for all typical values. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter test conditions t a = -40c to 85c units min typ max
isl5857 6 fn6079.3 october 7, 2015 submit document feedback digital inputs d11-d0, clk input logic high voltage with 3.3v supply, v ih ( note 5 ) 2.3 3.3 - v input logic low voltage with 3.3v supply, v il ( note 5 )-0 1.0 v sleep input current, i ih -25 - +25 a input logic current, i ih, i il -20 - +20 a clock input current, i ih, i il -10 - +10 a digital input capacitance, c in -5 - pf timing characteristics data setup time, t su see figure 17 -1.5 - ns data hold time, t hld see figure 17 -1.5 - ns propagation delay time, t pd see figure 17 -1 -clock period clk pulse width, t pw1 , t pw2 see figure 17 ( note 5 ) 0.9 --ns power supply characteristics av dd power supply ( note 11 ) 2.7 3.3 3.6 v dv dd power supply ( note 11 ) 2.7 3.3 3.6 v analog supply current (i avdd ) 3.3v, ioutfs = 20ma - 27.5 28.5 ma 3.3v, ioutfs = 2ma - 10 - ma digital supply current (i dvdd )3.3v ( note 7 ) - 3.7 5 ma 3.3v ( note 8 ) - 6.5 8 ma supply current (i avdd ) sleep mode 3.3v, ioutfs = don?t care - 1.5 - ma power dissipation 3.3v, ioutfs = 20ma ( note 7 )-103 111 mw 3.3v, ioutfs = 20ma ( note 8 )-110 120 mw 3.3v, ioutfs = 20ma ( note 9 )-157-mw 3.3v, ioutfs = 2ma ( note 7 ) - 45 - mw power supply rejection single supply ( note 10 ) -0.125 - +0.125 %fsr/v notes: 4. gain error measured as the error in the ratio between the full scale output current and the current through r set (typically 625a). ideally the ratio should be 32. 5. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. 6. spectral measurements made with differen tial transformer coupled output and no external filtering. for multitone testing, the same pattern was used at different clock rates, producing different output frequencies but at the same ratio to the clock rate. 7. measured with the clock at 130msps and the output frequency at 5mhz. 8. measured with the clock at 200msps and the output frequency at 20mhz. 9. measured with the clock at 260msps and the output frequency at 40mhz. 10. see ? definition of specifications ? on page 9 . 11. recommended operation is from 3.0v to 3.6v. operation below 3. 0v is possible with some degradation in spectral performance. reduction in analog output current may be necessary to maintain spectral performance. 12. see ? typical performance plots ? on page 7 . electrical specifications av dd = dv dd = +3.3v, v ref = internal 1.2v, ioutfs = 20ma, t a = +25c for all typical values. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter test conditions t a = -40c to 85c units min typ max
isl5857 7 fn6079.3 october 7, 2015 submit document feedback typical performance plots (+3.3v supply, using figure 15 with r diff = 100 and r load = 50 ) figure 3. edge at 11mhz, 78msps clock (91+dbc at ? f = +6mhz) figure 4. edge at 11mhz, 78msps clock (75dbc -nyquist, 6db pad) figure 5. gsm at 11mhz, 78msps clock (90+dbc at ? f = +6mhz, 3db pad) figure 6. gsm at 11mhz, 78msps clock (75dbc - nyquist, 9db pad) figure 7. four edge carriers at 12.4 to 15.6mhz, 800khz spacing, 78msps (71dbc - 20mhz window) figure 8. four gsm carriers at 12.4 to 15.6mhz, 78msps (73dbc - 20mhz window, 6db pad) spectral mask for gsm900/dcs1800/pcs1900 p>43dbm normal bts with 30khz rbw spectral mask for gsm900/dcs1800/pcs1900 p>43dbm normal bts with 30khz rbw
isl5857 8 fn6079.3 october 7, 2015 submit document feedback figure 9. umts at 19.2mhz, 76.8msps (70db 1st acpr, 70db 2nd acpr) figure 10. one tone at 10.1mhz, 80msps clock (71dbc - nyquist, 6db pad) figure 11. one tone at 40.4mhz, 210msps clock (61dbc - nyquist, 6db pad) figure 12. eight tones (crest factor = 8.9) at 37mhz, 210msps clock, 2.1mhz spacing (65dbc - nyquist) figure 13. two tones (cf = 6) at 8.5mhz, 50msps clock, 500khz spacing (82dbc - 10mhz window, 6db pad) figure 14. four tones (cf = 8. 1) at 14mhz, 80msps clock, 800khz spacing (70dbc - nyquist, 6db pad) typical performance plots (+3.3v supply, using figure 15 with r diff = 100 and r load = 50 ) (continued) spectral mask umts tdd p>43dbm bts
isl5857 9 fn6079.3 october 7, 2015 submit document feedback definition of specifications adjacent channel power ratio, acpr, is the ratio of the average power in the adjacent frequency channel (or offset) to the average power in the transmitted frequency channel. differential linearity error, dnl, is the measure of the step size output deviation from code to co de. ideally the step size should be 1 lsb. a dnl specification of 1 lsb or less guarantees monotonicity. edge, enhanced data for global evolution, a tdma standard for cellular applications which uses 200khz bw, 8-psk modulated carriers. full scale gain drift, is measured by setting the data inputs to be all logic high (all 1s) and measuring the output voltage through a known resistance as th e temperature is varied from t min to t max . it is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm of fsr (full scale range) per c. full scale gain error , is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through r set ). gsm, global system for mobile communication, a tdma standard for cellular applicat ions which uses 200khz bw, gmsk modulated carriers. integral linearity error, inl, is the measure of the worst case point that deviates from a best fi t straight line of data values along the transfer curve. internal reference voltage drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm per c. offset drift, is measured by setting the data inputs to all logic low (all 0s) and measuring the ou tput voltage at iouta through a known resistance as the te mperature is varied from t min to t max . it is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm of fsr (full scale range) per c. offset error, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage of iouta through a known resistance. offset erro r is defined as the maximum deviation of the iouta output current from a value of 0ma. output voltage compliance range, is the voltage limit imposed on the output. the output impedance should be chosen such that the voltage developed does not violate the compliance range. power supply rejection, is measured using a single power supply. the nominal supply voltage is varied 10% and the change in the dac full scale output is noted. reference input multiplying bandwidth, is defined as the 3db bandwidth of the voltage reference input. it is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. the frequency is increased until the amplitude of the output waveform is 0.707 (-3db) of its original value. spurious free dynamic range, sfdr , is the amplitude difference from the fundamental signal to the largest harmonically or non-harmonical ly related spur within the specified frequency window. total harmonic distortion, thd, is the ratio of the rms value of the fundamental output signal to the rms sum of the first five harmonic components. umts, universal mobile telecommunications system, a w-cdma standard for cellular applications which uses 3.84mhz modulated carriers. detailed description the isl5857 is a 12-bit, current out, cmos, digital to analog converter. the maximum update rate is at least 260+msps and can be powered by a single power supply in the recommended range of +3.0v to +3.6v. it consumes less than 120mw of power when using a +3.3v supply, the maximum 20ma of output current, and the data switching at 210msps. the architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. in previous architectures that contained all binary weight ed current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain worst-case transition points, such as midscale and quarter scale transitions. by gr eatly reducing the amount of current switching at these major transitions, the overall glitch of the converter is dramatically reduced, improving settling time, transient problems and accuracy. digital inputs and termination the isl5857 digital inputs ar e guaranteed to 3v lvcmos levels. the internal register is updated on the rising edge of the clock. to minimize reflections, proper termination should be implemented. if the lines driving the clock and the digital inputs are long 50 lines, then 50 termination resistors should be placed as close to the converter inputs as possible connected to the digital ground plane (if separate grounds are used). these termination resist ors are not likely needed as long as the digital waveform sour ce is within a few inches of the dac. for pattern drivers with very high speed edge rates, it is recommended that the user consider series termination (50 to 200 ?? prior to the dac?s inputs in order to reduce the amount of noise. power supply separate digital and analog po wer supplies are recommended. the allowable supply range is +2.7v to +3.6v. the recommended supply range is +3.0v to 3.6v (nominally +3.3v) to maintain optimum sfdr. however, operation down to +2.7v is possible with some degrad ation in sfdr. reducing the analog output current can help the sfdr at +2.7v. the sfdr values stated in the table of specifications were obtained with a +3.3v supply.
isl5857 10 fn6079.3 october 7, 2015 submit document feedback ground planes separate digital and analog ground planes should be used. all of the digital functions of the device and their corresponding components should be located over the digital ground plane and terminated to the digital ground plane. the same is true for the analog components an d the analog ground plane. noise reduction to minimize power supply noise, 0.1f capacitors should be placed as close as possible to the converter?s power supply pins, av dd and dv dd . also, the layout should be designed using separate digital and anal og ground planes and these capacitors should be terminated to the digital ground for dv dd and to the analog ground for av dd . additional filtering of the power supplies on the board is recommended. voltage reference the internal voltage reference of the device has a nominal value of +1.23v with a 40ppm/c drift coefficient over the full temperature range of the converte r. it is recommended that a 0.1f capacitor be placed as close as possible to the refio pin, connected to the analog ground. the reflo pin (16) selects the reference. the internal reference can be selected if pin 16 is tied low (ground). if an external reference is desired, then pin 16 should be tied high (the analog supply voltage) and the external reference driven into refio, pin 17. the full scale output current of the converter is a function of the voltage reference used and the value of r set . i out should be within the 2ma to 20ma range, thou gh operation below 2ma is possible with performance degradation. if the internal reference is used, v fsadj will equal approximately 1.2v (pin 18). if an external reference is used, v fsadj will equal the external reference. the calculation for i out (full scale) is: i out (full scale) = (v fsadj /r set) x 32 if the full scale output current is set to 20ma by using the internal voltage reference (1.2v) and a 1.91k r set resistor, then the input coding to output current will resemble the following: analog output iouta and ioutb are complement ary current outputs. the sum of the two currents is always equal to the full scale output current minus one lsb. if single-ended use is desired, a load resistor can be used to convert the output current to a voltage. it is recommended that the unus ed output be either grounded or equally terminated. the voltage developed at the output must not violate the output voltage compliance range of -1.0v to 1.25v. r out (the impedance loading each current output) should be chosen so that th e desired output voltage is produced in conjunction with th e output full scale current. if a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. the output voltage equation is: v out = i out x r out . the most effective method for reducing the power consumption is to reduce the analog output current, which dominates the supply current. the maximum recommended output current is 20ma. differential output iouta and ioutb can be used in a differential-to-single-ended arrangement to achieve better harmonic rejection. with r diff = 50 ? and r load = 50 , the circuit in figure 15 will provide a 500mv signal at the outp ut of the transformer if the full scale output current of the dac is set to 20ma (used for the electrical specifications table). values of r diff = 100 ? and r load = 50 were used for the typical performance curves. the center tap in figure 15 must be grounded. in the circuit in figure 16 , the user is left with the option to ground or float the center tap. the dc voltage that will exist at either iouta or ioutb if the center tap is floating is iout dc x (r a //r b ) v because r diff is dc shorted by the transformer. if the center tap is grounded, the dc voltage is 0v. recommended values for the circuit in figure 16 are r a =r b = 50 , r diff = 100 , assuming r load = 50 . the performance of figures 15 and 16 is basically the same, however leaving the center tap of figure 16 floating allows the circuit to find a more balanced virtual ground, theoretically improving the even order harmonic rejection, but likely reducing the signal swing available due to the output voltage compliance range limitations. table 1. input coding vs output current with internal reference and rset = 1.91k input code (d11-d0) iouta (ma) ioutb (ma) 11 11111 11111 20 0 10 00000 00000 10 10 00 00000 00000 0 20
isl5857 11 fn6079.3 october 7, 2015 submit document feedback propagation delay the converter requires two clock rising edges for data to be represented at the output. each rising edge of the clock captures the present data word and outputs the previous data. the propagation delay is ther efore 1/clk, plus <2ns of processing. see figure 17 . test service intersil offers customer-specific testing of converters with a service called testdrive. to submit a request, fill out the testdrive form. the form can be found by doing an ?entire site search? at www.intersil.com on the words ?dac testdrive?. or, send a request to the technical support center. figure 15. output loading for datasheet measurements pin 21 pin 22 r diff isl5857 r load ioutb iouta v out = (2 x iouta x r eq )v load seen by the transformer r load represents the 1:1 r eq = 0.5 x (r load //r diff ) at each output figure 16. alternative output loading pin 21 pin 22 isl5857 ioutb iouta v out = (2 x iouta x r eq )v r eq = 0.5 x (r load //r diff //r a ), where r a = r b at each output r load r diff r a r b load seen by the transformer r load represents the timing diagram figure 17. propagation delay, setup time, hold time and minimum pulse width diagram clk i out 50% t pw1 t pw2 t su t hld t su t su t pd t hld t hld d11-d0 w 0 w 1 w 2 w 3 output = w 0 output = w 1 t pd output = w -1
isl5857 12 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6079.3 october 7, 2015 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change october 7, 2015 fn6079.3 updated ordering information on page 3. may 14, 2015 fn6079.2 updated entire datasheet applying intersil?s new standards. moved the typical application circuit to page 1, pin conf iguration to page 2, and ordering information table to page 3. removed obsolete products from the ordering information table on page 3. added notes 2 and 3 to the ordering information table. added the part marking column to the ordering information table. removed (-2.5dbm) from the following sentence unde r ?differential output? on page 10: ?with rdiff = 50 and rload = 50 , the circuit in figure 13 will provid e a 500mv (-2.5dbm) sign al at the output of the transformer if the full scale output current of the dac is set to 20ma (used for the electrical specifications table).? added revision history and about intersil verbiage updated pod m28.3 to latest revision. -change made from rev 0 to rev 1 was adding land pattern updated pod m28.173 to latest revision. -changes made from rev 0 to rev 1 was converting to new pod format by moving dimensions from table onto drawing and adding land patt ern. no dimension changes.
isl5857 13 fn6079.3 october 7, 2015 submit document feedback small outline plast ic packages (soic) a index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45o c h 0.25(0.010) b m m (1.50mm) (9.38mm) (1.27mm typ) (0.51mm typ) typical recommended land pattern m28.3 (jedec ms-013-ae issue c ) 28 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.6969 0.7125 17.70 18.10 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n28 287 ? 0 o 8 o 0 o 8 o - rev. 1, 1/13 notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gat e burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm ( 0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions . interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greate r above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact .
isl5857 14 fn6079.3 october 7, 2015 submit document feedback package outline drawing m28.173 28 lead thin shrink small outline package (tssop) rev 1, 5/10 detail "x" typical recommended land pattern top view side view end view dimension does not include mold flash, protrusions or gate burr s. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension does not include inter lead flash or protrusion. inter lead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. dimensioning and tolerancing per asme y14.5m-1994. dimension does not include dambar protrusion. allowable protrus ion shall be 0.08mm total in excess of dimension at maximum materia l condition. minimum space between protrusion and adjacent lead is 0.07mm. dimension in ( ) are for reference only. conforms to jedec mo-153. 6. 3. 5. 4. 2. 1. notes: 7. 5 seating plane c h 3 2 1 28 b 14 1 3 15 a plane gauge 0.05 min 0.15 max 0-8 0.60 0.15 0.90 1.00 ref 0.25 see detail "x" 0.25 (0.65 typ) (5.65) (0.35 typ) (1.45) 6.40 4.40 0.10 0.65 1.20 max pin #1 i.d. mark 9.70 0.10 -0.06 0.15 +0.05 -0.10 +0.15 -0.06 +0.05 0.20 c b a 0.10 c - 0.05 0.10 c b a m

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